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mc145053 motorola wireless semiconductor solutions device data 1
cmos this ratiometric 10-bit adc has a serial interface port to provide communi- cation with mcus and mpus. either a 10- or 16-bit format can be used . the 16-bit format can be one continuous 16-bit stream or two intermittent 8-bit streams. the converter operates from a single power supply with no external trimming required. reference voltages down to 4.0 v are accommodated. the mc145053 has an internal clock oscillator to operate the dynamic a/d conversion sequence and an end-of-conversion (eoc) output. ? 5 analog input channels with internal sample-and-hold ? operating temperature range: 40 to 125 c ? successive approximation conversion time: 44 m s maximum ? maximum sample rate: 20.4 ks/s ? analog input range with 5-volt supply: 0 to 5 v ? monotonic with no missing codes ? direct interface to motorola spi and national microwire serial data ports ? digital inputs/outputs are ttl, nmos, and cmos compatible ? low power consumption: 14 mw ? chip complexity: 1630 elements (fets, capacitors, etc.) ? see application note an1062 for operation with qspi block diagram successive approximation register 2 3 4 5 6 12 11 1 10 13 10-bit rc dac with sample and hold data register 98 v ag v ref auto-zeroed comparator mux address register digital control logic internal test voltages an0 an1 an2 an3 an4 an5 an6 an7 cs d in d out sclk eoc mux out pin 14 = v dd pin 7 = v ss analog mux microwire is a trademark of national semiconductor corp. order this document by mc145053/d semiconductor technical data pin assignment
p suffix plastic case 646 d suffix sog case 751a ordering information mc145053p plastic dip MC145053D sog package 11 12 13 14 8 9 10 5 4 3 2 1 7 6 cs d out d in sclk v dd v ag v ref an2 an1 an0 eoc v ss an4 an3 ? motorola, inc. 1998 rev 2 1/99
mc145053 motorola wireless semiconductor solutions device data 2 maximum ratings* symbol parameter value unit v dd dc supply voltage (referenced to v ss ) 0.5 to + 6.0 v v ref dc reference voltage v ag to v dd + 0.1 v v ag analog ground v ss 0.1 to v ref v v in dc input voltage, any analog or digital input v ss 0.5 to v dd + 0.5 v v out dc output voltage v ss 0.5 to v dd + 0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 25 ma i dd , i ss dc supply current, v dd and v ss pins 50 ma t stg storage temperature 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c * maximum ratings are those values beyond which damage to the device may occur. func- tional operation should be restricted to the operation ranges below.. operation ranges (applicable to guaranteed limits) symbol parameter value unit v dd dc supply voltage, referenced to v ss 4.5 to 5.5 v v ref dc reference voltage v ag + 4.0 to v dd + 0.1 v v ag analog ground v ss 0.1 to v ref 4.0 v v ai analog input voltage (see note) v ag to v ref v v in , v out digital input voltage, output voltage v ss to v dd v t a ambient operating temperature 40 to 125 c note: analog input voltages greater than v ref convert to full scale. input voltages less than v ag convert to zero. see v ref and v ag pin descriptions. dc electrical characteristics (voltages referenced to v ss , full temperature and voltage ranges per operation ranges table, unless otherwise indicated) symbol parameter test condition guaranteed limit unit v ih minimum high-level input voltage (d in , sclk, cs ) 2.0 v v il maximum low-level input voltage (d in , sclk, cs ) 0.8 v v oh minimum high-level output voltage (d out , eoc) i out = 1.6 ma i out = 20 m a 2.4 v dd 0.1 v v ol minimum low-level output voltage (d out , eoc) i out = + 1.6 ma i out = + 20 m a 0.4 0.1 v i in maximum input leakage current (d in , sclk, cs ) v in = v ss or v dd 2.5 m a i oz maximum three-state leakage current (d out ) v out = v ss or v dd 10 m a i dd maximum power supply current v in = v ss or v dd , all outputs open 2.5 ma i ref maximum static analog reference current (v ref ) v ref = v dd , v ag = v ss 100 m a i al maximum analog mux input leakage current between all deselected inputs and any selected input (an0 an4) v al = v ss to v dd 1 m a this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, pre- cautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open.
mc145053 motorola wireless semiconductor solutions device data 3 a/d converter electrical characteristics (full temperature and voltage ranges per operation ranges table) characteristic definition and test conditions guaranteed limit unit resolution number of bits resolved by the a/d converter 10 bits maximum nonlinearity maximum difference between an ideal and an actual adc transfer function 1 lsb maximum zero error difference between the maximum input voltage of an ideal and an actual adc for zero output code 1 lsb maximum full-scale error difference between the minimum input voltage of an ideal and an actual adc for full-scale output code 1 lsb maximum total unadjusted error maximum sum of nonlinearity, zero error, and full-scale error 1 lsb maximum quantization error uncertainty due to converter resolution 1/2 lsb absolute accuracy difference between the actual input voltage and the full-scale weighted equivalent of the binary output code, all error sources included 1-1/2 lsb maximum conversion time total time to perform a single analog-to-digital conversion 44 m s data transfer time total time to transfer digital serial data into and out of the device 10 to 16 sclk cycles sample acquisition time analog input acquisition time window 6 sclk cycles minimum total cycle time total time to transfer serial data, sample the analog input, and perform the conversion; sclk = 2.1 mhz 49 m s maximum sample rate rate at which analog inputs may be sampled; sclk = 2.1 mhz 20.4 ks/s
mc145053 motorola wireless semiconductor solutions device data 4 ac electrical characteristics (full temperature and voltage ranges per operation ranges table) figure symbol parameter guaranteed limit unit 1 f clock frequency, sclk (10-bit xfer) min (11- to 16-bit xfer) min note: refer to t wh , t wl below (10- to 16-bit xfer) max) 0 note 1 2.1 mhz 1 t wh minimum clock high time, sclk 190 ns 1 t wl minimum clock low time, sclk 190 ns 1, 7 t plh , t phl maximum propagation delay, sclk to d out 125 ns 1, 7 t h minimum hold time, sclk to d out 10 ns 2, 7 t plz , t phz maximum propagation delay, cs to d out high-z 150 ns 2, 7 t pzl , t pzh maximum propagation delay, cs to d out driven 2.3 m s 3 t su minimum setup time, d in to sclk 100 ns 3 t h minimum hold time, sclk to d in 0 ns 4, 7, 8 t d maximum delay time, eoc to d out (msb) 100 ns 5 t su minimum setup time, cs to sclk 2.425 m s e t csd minimum time required between 10th sclk falling edge ( 0.8 v) and cs to allow a conversion note 2 e t cas maximum delay between 10th sclk falling edge ( 2 v) and cs to abort a conversion 9 m s 5 t h minimum hold time, last sclk to cs 0 ns 6, 8 t phl maximum propagation delay, 10th sclk to eoc 2.35 m s 1 t r , t f maximum input rise and fall times sclk d in , cs 1 10 ms m s 1, 4, 6 8 t tlh , t thl maximum output transition time, any output 300 ns e c in maximum input capacitance an0 an4 sclk, cs , d in 55 15 pf e c out maximum three-state output capacitance d out 15 pf notes: 1. after the 10th sclk falling edge ( 2 v), at least 1 sclk rising edge ( 2 v) must occur within 18.5 m s. 2. a cs edge may be received immediately after an active transition on the eoc pin.
mc145053 motorola wireless semiconductor solutions device data 5 switching waveforms d out sclk 0.8 v 2.0 v 0.4 v 2.4 v t wl t wh 1/f t r t f t h t plh , t phl t tlh , t thl figure 1. 0.4 v 2.4 v t phz , t plz 0.8 v 2.0 v d out cs t pzh , t pzl 90% 10% figure 2. t h 0.8 v 2.0 v t su valid sclk d in 0.8 v 2.0 v figure 3. note: d out is driven only when cs is active (low). 0.4 v 2.4 v valid msb d out eoc t tlh t d 0.4 v 2.4 v figure 4. 2.0 v 0.8 v 0.8 v 0.8 v t h t su first clock last clock cs sclk figure 5. 0.4 v 2.4 v 0.8 v t phl 10th clock eoc sclk t thl figure 6. test point device under test v dd d out 12 k 100 pf 2.18 k figure 7. test circuit test point device under test v dd eoc 12 k 50 pf 2.18 k figure 8. test circuit
mc145053 motorola wireless semiconductor solutions device data 6 pin descriptions digital inputs and output the various serial bit-stream formats for the mc145053 are illustrated in the timing diagrams of figures 9 through 14. table 1 assists in selection of the appropriate diagram. note that the adc accepts 16 clocks which makes it spi (serial peripheral interface) compatible. table 1. timing diagram selection no. of clocks in serial transfer using cs serial transfer interval figure no. 10 yes don't care 9 10 no don't care 10 11 to 16 yes shorter than conversion 11 16 no shorter than conversion 12 11 to 16 yes longer than conversion 13 16 no longer than conversion 14 cs active-low chip select input (pin 10) chip select initializes the chip to perform conversions and provides 3-state control of the data output pin (d out ). while inactive high, cs forces d out to the high-impedance state and disables the data input (d in ) and serial clock (sclk) pins. a high-to-low transition on cs resets the serial data port and synchronizes it to the mpu data stream. cs can re- main active during the conversion cycle and can stay in the active low state for multiple serial transfers or cs can be in- active high after each transfer. if cs is kept active low be- tween transfers, the length of each transfer is limited to either 10 or 16 sclk cycles. if cs is in the inactive high state be- tween transfers, each transfer can be anywhere from 10 to 16 sclk cycles long. see the sclk pin description for a more detailed discussion of these requirements. spurious chip selects caused by system noise are mini- mized by the internal circuitry. any transitions on the cs pin are recognized as valid only if the level is maintained for about 2 m s after the transition. note if cs is inactive high after the 10th sclk cycle and then goes active low before the a/d conver- sion is complete, the conversion is aborted and the chip enters the initial state, ready for another serial transfer/conversion sequence. at this point, the output data register contains the result from the conversion before the aborted conversion. note that the last step of the a/d conversion se- quence is to update the output data register with the result. therefore, if cs goes active low in an attempt to abort the conversion too close to the end of the conversion sequence, the result regis- ter may be corrupted and the chip could be thrown out of sync with the processor until cs is toggled again (refer to the ac electrical characteristics in the spec tables). d out serial data output of the a/d conversion result (pin 11) this output is in the high-impedance state when cs is in- active high. when the chip recognizes a valid active low on cs , d out is taken out of the high-impedance state and is driv- en with the msb of the previous conversion result. (for the first transfer after power-up, data on d out is undefined for the entire transfer.) the value on d out changes to the second most significant result bit upon the first falling edge of sclk. the remaining result bits are shifted out in order, with the lsb appearing on d out upon the ninth falling edge of sclk. note that the order of the transfer is msb to lsb. upon the 10th falling edge of sclk, d out is immediately driven low (if allowed by cs ) so that transfers of more than 10 sclks read zeroes as the unused lsbs. when cs is held active low between transfers, d out is driv- en from a low level to the msb of the conversion result for three cases: case 1 e upon the 16th sclk falling edge if the transfer is longer than the conversion time (figure 14); case 2 e upon completion of a conversion for a 16-bit trans- fer interval shorter than the conversion (figure 12); case 3 e upon completion of a conversion for a 10-bit transfer (fig- ure 10). d in serial data input (pin 12) the four-bit serial input stream begins with the msb of the analog mux address (or the user test mode) that is to be con- verted next. the address is shifted in on the first four rising edges of sclk. after the four mux address bits have been received, the data on d in is ignored for the remainder of the present serial transfer. see table 2 in applications in- formation . sclk serial data clock (pin 13) this clock input drives the internal i/o state machine to perform three major functions: (1) drives the data shift regis- ters to simultaneously shift in the next mux address from the d in pin and shift out the previous conversion result on the d out pin, (2) begins sampling the analog voltage onto the rc dac as soon as the new mux address is available, and (3) transfers control to the a/d conversion state machine after the last bit of the previous conversion result has been shifted out on the d out pin. the serial data shift registers are completely static, allow- ing sclk rates down to the dc. there are some cases, how- ever, that require a minimum sclk frequency as discussed later in this section. at least ten sclk cycles are required for each simultaneous data transfer. if the 16-bit format is used, sclk can be one continuous 16-bit stream or two intermit- tent 8-bit streams. after the serial port has been initiated to perform a serial transfer*, the new mux address is shifted in * the serial port can be initiated in three ways: (1) a recognized cs falling edge, (2) the end of an a/d conversion if the port is perform- ing either a 10-bit or a 16-bit ashorter-than-conversiono transfer with cs active low between transfers, and (3) the 16th falling edge of sclk if the port is performing 16-bit alonger-than-conversiono transfers with cs active low between transfers.
mc145053 motorola wireless semiconductor solutions device data 7 on the first four rising edges of sclk, and the previous 10-bit conversion result is shifted out on the first nine falling edges of sclk. after the fourth rising edge of sclk, the new mux address is available; therefore, on the next edge of sclk (the fourth falling edge), the analog input voltage on the selected mux input begins charging the rc dac and con- tinues to do so until the tenth falling edge of sclk. after this tenth sclk edge, the analog input voltage is disabled from the rc dac and the rc dac begins the aholdo portion of the a/d conversion sequence. also upon this tenth sclk edge, control of the internal circuitry is transferred to the internal clock oscillator which drives the successive approximation logic to complete the conversion. if 16 sclk cycles are used during each transfer, then there is a constraint on the mini- mum sclk frequency. specifically, there must be at least one rising edge on sclk before the a/d conversion is com- plete. if the sclk frequency is too low and a rising edge does not occur during the conversion, the chip is thrown out of sync with the processor and cs needs to be toggled in or- der to restore proper operation. if 10 sclks are used per transfer, then there is no lower frequency limit on sclk. also note that if the adc is operated such that cs is inactive high between transfers, then the number of sclk cycles per transfer can be anything between 10 and 16 cycles, but the arising edgeo constraint is still in effect if more than 10 sclks are used. (if cs stays active low for multiple transfers, the number of sclk cycles must be either 10 or 16.) eoc end-of-conversion output (pin 1) eoc goes low on the tenth falling edge of sclk. a low-to- high transition on eoc occurs when the a/d conversion is complete and the data is ready for transfer. analog inputs and test modes an0 through an4 analog multiplexer inputs (pins 2 6) the input an0 is addressed by loading $0 into the mux address register. an1 is addressed by $1, an2 by $2, an3 by $3, and an4 by $4. table 2 shows the input format for a 16-bit stream. the mux features a break-before-make switching structure to minimize noise injection into the ana- log inputs. the source resistance driving these inputs must be 1 k w . during normal operation, leakage currents through the analog mux from unselected channels to a selected channel and leakage currents through the esd protection diodes on the selected channel occur. these leakage currents cause an offset voltage to appear across any series source resis- tance on the selected channel. therefore, any source resis- tance greater than 1 k w (motorola test condition) may induce errors in excess of guaranteed specifications. there are three tests available that verify the functionality of all the control logic as well as the successive approxima- tion comparator. these tests are performed by addressing $b, $c, or $d and they convert a voltage of (v ref + v ag )/2, v ag , or v ref , respectively. the voltages are obtained internal- ly by sampling v ref or v ag onto the appropriate elements of the rc dac during the sample phase. addressing $b, $c, or $d produces an output of $200 (half scale), $000, or $3ff (full scale), respectively, if the converter is functioning prop- erly. however, deviation from these values occurs in the presence of sufficient system noise (external to the chip) on v dd , v ss , v ref , or v ag . power and reference pins v ss and v dd device supply pins (pins 7 and 14) v ss is normally connected to digital ground; v dd is con- nected to a positive digital supply voltage. low frequency (v dd v ss ) variations over the range of 4.5 to 5.5 volts do not affect the a/d accuracy. (see the operations ranges table for restrictions on v ref and v ag relative to v dd and v ss .) excessive inductance in the v dd or v ss lines, as on automatic test equipment, may cause a/d offsets > 1 lsb. use of a 0.1 m f bypass capacitor across these pins is recom- mended. v ag and v ref analog reference voltage pins (pins 8 and 9) analog reference voltage pins which determine the lower and upper boundary of the a/d conversion. analog input volt- ages v ref produce a full scale output and input voltages v ag produce an output of zero. caution: the analog input voltage must be v ss and v dd . the a/d conversion result is ratiometric to v ref v ag . v ref and v ag must be as noise-free as possible to avoid degradation of the a/d conversion. ideally, v ref and v ag should be single-point con- nected to the voltage supply driving the system's transduc- ers. use of a 0.22 m f bypass capacitor across these pins is strongly urged.
mc145053 motorola wireless semiconductor solutions device data 8 d out sclk d in eoc cs a/d conversion interval sample analog input re-initialize initialize high impedance d9 msb msb a3 a2 a1 a0 shift in new mux address, simultaneously shift out previous conversion value 12345678910 1 d8 d7 d6 d5 d4 d3 d2 d1 d0 d9 a3 figure 9. timing for 10-clock transfer using cs a/d conversion interval shift in new mux address, simultaneously shift out previous conversion value msb 1 2345678910 1 d out sclk d in eoc cs sample analog input low level d9 msb d8 d7 d6 d5 d4 d3 d2 d1 d0 d9 initialize must be high on power up a3 a2 a1 a0 a3 figure 10. timing for 10-clock transfer not using cs notes: 1. d9, d8, d7, d6, d5, , d0 = the result of the previous a/d conversion. 2. a3, a2, a1, a0 = the mux address for the next a/d conversion.
mc145053 motorola wireless semiconductor solutions device data 9 d in initialize d out a/d conversion interval eoc sclk d9 msb d8 d7 d6 d5 d4 d3 d2 d1 d0 1234 567891011 16 low level 1 sample analog input msb d9 12 13 14 15 must be high on power up cs notes: d9, d8, d7, . . . , d0 = the result of the previous a/d conversion. a3, a2, a1, a0 = the mux address for the next a/d conversion. *this figure illustrates the behavior of the mc145051. the mc145050 behaves identically except there is no eoc signal and the conversion time is 44 adclk cycles (user-controlled time). figure 12. timing for 16-clock transfer not using cs* (serial transfer interval shorter than conversion) d in initialize d out a/d conversion eoc sclk cs d8 d7 d6 d5 d4 d3 d2 d1 d0 1 23 456789101116 low impedance sample analog input a3 a2 a1 a0 re-initialize shift in new mux address, high simultaneously shift out previous conversion value level 1 d9 a3 interval figure 11. timing for 11- to 16-clock transfer using cs* (serial transfer interval shorter than conversion) shift in new mux address, simultaneously shift out previous conversion value d9 msb a3 a3 a2 a1 a0
mc145053 motorola wireless semiconductor solutions device data 10 figure 13. timing for 11- to 16-clock transfer using cs* (serial transfer interval longer than conversion) figure 14. timing for 16-clock transfer not using cs* (serial transfer interval longer than conversion) d in initialize d out eoc sclk d8 d7 d6 d5 d4 d3 d2 d1 d0 1 23 456789101116 low impedance re-initialize shift in new mux address, high simultaneously shift out previous conversion value level 1 d9 cs note 2 sample analog input d in initialize d out eoc sclk d8 d7 d6 d5 d4 d3 d2 d1 d0 1234567891011 16 low level 1 sample analog input msb shift in new mux address, d9 12 13 14 15 simultaneously shift out previous conversion value must be high on power up cs a/d conversion interval notes: a3, a2, a1, a0 = the mux address for the next a/d conversion. *notes: 1. this figure illustrates the behavior of the mc145051. the mc145050 behaves identically except there is no eoc signal and the conversion time is 44 adclk cycles (user-controlled time). 2. the 11th sclk rising edge must occur before the conversion is complete. otherwise the serial port is thrown out of sync with the microprocessor for the remainder of the transfer. note 2 a/d conversion interval d9 msb d9 msb a3 a3 a3 a2 a1 a0 a3 a2 a1 a0 d9, d8, d7, . . . , d0 = the result of the previous a/d conversion.
mc145053 motorola wireless semiconductor solutions device data 11 applications information description this example application of the mc145053 adc interfaces four analog signals to a microprocessor. figure 15 illustrates how the mc145053 is used as a cost- effective means to simplify this type of circuit design. utilizing one adc, four analog inputs are interfaced to a cmos or nmos microprocessor with a serial peripheral interface (spi) port. processors with national semiconductor's microwire serial port may also be used. full duplex operation optimizes throughput for this system. digital design considerations motorola's mc68hc05c4 cmos mcu may be chosen to reduce power supply size and cost. the nmos mcus may be used if power consumption is not critical. a v dd or v ss 0.1 m f bypass capacitor should be closely mounted to the adc. the mc145053 has the end-of-conversion (eoc) signal at output pin 1 to define when data is ready. analog design considerations analog signal sources with output impedances of less than 1 k w may be directly interfaced to the adc, eliminating the need for buffer amplifiers. separate lines connect the v ref and v ag pins on the adc with the controllers to provide isolation from system noise. although not indicated in figure 15, the v ref and sensor output lines may need to be shielded, depending on their length and electrical environment. this should be verified during prototyping with an oscilloscope. if shielding is required, a twisted pair or foil-shielded wire (not coax) is appropriate for this low frequency application. one wire of the pair or the shield must be v ag . a reference circuit voltage of 5 volts is used for the applica- tion shown in figure 15. however, the reference circuitry may be simplified by tying v ag to system ground and v ref to the system's positive supply. (see figure 16.) a bypass capacitor of approximately 0.22 m f across the v ref and v ag pins is recommended. these pins are adjacent on the adc package which facilitates mounting the capacitor very close to the adc. software considerations the software flow for acquisition is straightforward. the four analog inputs, an0 through an3, are scanned by read- ing the analog value of the previously addressed channel into the mcu and sending the address of the next channel to be read to the adc, simultaneously. the designer utilizing the mc145053 has the end-of-con- version signal (at pin 1) to define the conversion interval. eoc may be used to generate an interrupt, which is serviced by reading the serial data from the adc. the software flow should then process and format the data. when this adc is used with a 16-bit (2-byte) transfer, there are two types of offsets involved. in the first type of offset, the channel information sent to the adcs is offset by 12 bits. that is, in the 16-bit stream, only the first 4 bits (4 msbs) contain the channel information. the balance of the bits are don't cares. this results in 3 don't-care nibbles, as shown in table 2. the second type of offset is in the conversion result returned from the adc; this is offset by 6 bits. in the 16-bit stream, the first 10 bits (10 msbs) contain the conversion result. the last 6 bits are zeroes. the hexadecimal result is shown in the first column of table 3. the second column shows the result after the offset is removed by a micro- processor routine. if the 16-bit format is used, the adc can transfer one continuous 16-bit stream or two intermittent 8-bit streams.
mc145053 motorola wireless semiconductor solutions device data 12 table 2. programmer's guide for 16-bit transfers: input code input address in hex channel to be converted next comment $0xxx $1xxx $2xxx $3xxx $4xxx $5xxx $6xxx $7xxx $8xxx $9xxx $axxx $bxxx $cxxx $dxxx $exxx $fxxx an0 an1 an2 an3 an4 none none none none none none an5 an6 an7 none none pin 2 pin 3 pin 4 pin 5 pin 6 not allowed not allowed not allowed not allowed not allowed not allowed half scale test: output = $8000 zero test: output = $0000 full scale test: output = $ffc0 not allowed not allowed table 3. programmer's guide for 16-bit transfers: output code conversion result without offset removed conversion result with offset removed value $0000 $0040 $0080 $00c0 $0100 $0140 $0180 $01c0 $0200 $0240 $0280 $02c0 $ff40 $ff80 $ffc0 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $03fd $03fe $03ff zero zero + 1 lsb zero + 2 lsbs zero + 3 lsbs zero + 4 lsbs zero + 5 lsbs zero + 6 lsbs zero + 7 lsbs zero + 8 lsbs zero + 9 lsbs zero + 10 lsbs zero + 11 lsbs full scale 2 lsbs full scale 1 lsb full scale 5 volt reference circuit analog sensors, etc. eoc d out sclk d in cs spi port an0 an1 an2 an3 an4 mc145053 adc m p 0.1 m f + 5 v v ss v dd v ref v ag 0.22 m f figure 15. example application
mc145053 motorola wireless semiconductor solutions device data 13 mc145053 v dd 5 v supply to sensors, etc. 0.1 m f 0.22 m f v ss v ref v ag do not connect at ic do not connect at ic digital + v analog + v digital gnd analog gnd figure 16. alternate configuration using the digital supply for the reference voltage compatible motorola mcus/mpus this is not a complete listing of motorola's mcus/mpus. contact your motorola representative if you need additional information. instruction memory (bytes) spi device instruction set rom eeprom spi sci device number m6805 2096 2096 4160 4160 8k 4160 8k 7700 e e e e e e e e e 4160 e yes yes yes yes yes yes yes e mc68hc05c2 mc68hc05c3 mc68hc05c4 mc68hsc05c4 mc68hsc05c8 mc68hcl05c4 mc68hcl05c8 mc68hc05c8 mc68hc805c4 m68000 e e e mc68hc000 spi = serial peripheral interface. sci = serial communication interface. high speed. low power.
mc145053 motorola wireless semiconductor solutions device data 14 package dimensions plastic dip p suffix case 646-06 18.16 6.10 3.69 0.38 1.02 1.32 0.20 2.92 0 0.39 19.56 6.60 4.69 0.53 1.78 2.41 0.38 3.43 10 1.01 2.54 bsc 7.62 bsc 0.715 0.240 0.145 0.015 0.040 0.052 0.008 0.115 0 0.015 seating plane 0.100 bsc 0.300 bsc min min max max inches millimeters dim 0.770 0.260 0.185 0.021 0.070 0.095 0.015 0.135 10 0.039 a b c d f g h j k l m n notes: 1. leads within 0.13 (0.005) radius of true position at seating plane at maximum material condition. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 4. rounded corners optional. 17 14 8 b a f hg d n k c l j m
mc145053 motorola wireless semiconductor solutions device data 15 sog package d suffix case 751a-03 min min max max millimeters inches dim a b c d f g j k m p r 8.55 3.80 1.35 0.35 0.40 0.19 0.10 0 5.80 0.25 8.75 4.00 1.75 0.49 1.25 0.25 0.25 7 6.20 0.50 0.337 0.150 0.054 0.014 0.016 0.008 0.004 0 0.228 0.010 0.344 0.157 0.068 0.019 0.049 0.009 0.009 7 0.244 0.019 1.27 bsc 0.050 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. -a- -b- p 7 pl g c k seat- ing plane d 14 pl m j r x 45 1 7 8 14 0.25 (0.010) t ba m s s b 0.25 (0.010) m m f motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : motorola japan ltd.; spd, strategic planning office, 141, p.o. box 5405, denver, colorado 80217. 13036752140 or 18004412447 4321 nishigotanda, shinagawaku, tokyo, japan. 81354878488 customer focus center: 18005216274 mfax ? : rmfax0@email.sps.mot.com touchtone 1 6022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, motorola fax back system us & canada only 18007741848 51 ting kok road, tai po, n.t., hong kong. 85226629298 http://sps.motorola.com/mfax/ home page : http://motorola.com/sps/ mc145053/d ?

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